FIG. 6 is a cross-sectional view of an n-channel vertical power MOSFET, generally denoted at 200, using a silicon substrate.
An n-type epitaxial layer 202 is formed on an n-type silicon substrate 201. Two p-type body regions 203 are formed in the epitaxial layer 202 by diffusion method. Also, an n-type doped layer 204 is formed in the each body region 203.
A source electrode 205 is formed on the n-type doped region 204. A gate electrode 207 is formed on the body region 203 provided between the epitaxial layer 202 and the n-type doped region 204 through an insulating layer 206. Also, a drain electrode 208 is formed on the back surface of the n-type silicon substrate 201.
In the vertical power MOSFET 200, the current flowing from the drain electrode 208 to the source electrode 205 is controlled by the voltage supplied to the gate electrode 207.
In the vertical power MOSFET 200, the withstand voltage between the source and drain electrodes is determined by the avalanche voltage of the pn junction between the p-type body region 203 and the epitaxial layer 202. Therefore, a limitation exists in the reduction of thickness of both body region 203 and epitaxial layer 202, because the avalanche breakdown increases as the voltage applied to the pn junction becomes larger. Consequently, the thickness of the vertical power MOSFET 200 is generally determined to about 600 μm.
On the other hand, an electrical isolation is needed between adjacent vertical power MOSFETs by forming an isolating region extending from the front surface to the back surface of the MOSFET, when a power semiconductor device having two vertical power MOSFETs of p-channel and n-channel formed together on the same substrate is formed. The isolating region is formed by the process of forming a trench which extends from the front surface of the MOSFET to the back surface of the substrate, and then filling the trench by silicon oxide or the like.
However, forming the narrow trench having the depth equal to the thickness of the MOSFET, e.g. 600 μm, is difficult. Consequently, it is difficult to form a plurality of vertical power MOSFETs on the same substrate, and therefore, the power semiconductor device is constructed of a plurality of vertical power MOSFETs which are individually fabricated.